1.0 Basic Networking Tasks
A networking hardware machine (e.g., a switch, a router, etc.) is usually designed to perform one or more basic networking tasks. One basic networking task may include a look-up, based upon a packet's header information, that classifies the packet. Another basic networking task is the management and implementation of one or more queues that can temporarily hold a packet (or at least a portion of a packet, or a control header that describes where a packet payload can be found in a memory device). FIG. 1 shows an example of a networking hardware line interface card (LIC) or “blade” 1011 that is designed to perform both of the aforementioned functions.
Note that the LIC 1011 also resides, as drawn within FIG. 1, within a networking hardware machine 100 such as a switch or router. In typical embodiments, the LIC 1011 receives “ingress” packets from a fiber optic or copper cable 1091 and also transmits “egress” packets over another fiber optic or copper cable 1081. Ingress/Egress circuitry 102 manages the physical reception and transmission of packets from/to the ingress/egress cables 1091/1081. As such, in the ingress direction, the ingress/circuitry 102 provides (e.g., along interface 113) a stream of data units (e.g., bytes, cells, words, etc.) to the network processing logic 103 that, together, represent one or more packets.
According to one design approach the ingress/circuitry 102 also performs packet delineation (i.e., the recognition of where a packet “starts” and/or “ends”) whereas, in another design approach, the network processing logic 102 performs packet delineation. Regardless, once the starting and/or ending point of a packet is recognized, the packet's header can be identified; and, subsequently, information that resides within the packet header can be used to perform a look-up. Network processing logic 103 is responsible for understanding the organization of the packet's header so that at least a portion of it (e.g., its source address, its source port, its destination address, its destination port, a connection identifier, a classification identifier, some combination of any or all of these, etc.) can be used as a basis for performing a look-up. In various embodiments, a search key is formed by the networking processing logic 102 from the specific packet header information.
The search key, which acts as a look-up input parameter, is then presented to a look-up resource 104. The look-up resource 104 stores information that is used to classify a packet so that the networking hardware machine 100 can treat the packet in an appropriate fashion. The look-up resource 104 can be implemented with a content addressable memory (CAM); and/or, a traditional memory such as a Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).
The look-up process may be performed, for each packet, with a single look-up (where the information that is used to help treat the packet appropriately is retrieved as an immediate response to the search key); or, alternatively a series of look-ups (e.g., a first look-up is performed from the search key to retrieve a reference value which; in turn, is used as a look-up parameter for a second look-up that produces the information used as guidance for treating the packet). The look-up resource 104 illustration of FIG. 1 is meant to generally depict any and/or all of the look-up resource devices used for the one or more look-ups that are performed. Furthermore, the interface between the network processing logic 103 and the look-up resource 104 may be bi-directional (as suggested by interface 110).
According to at least one approach, the information provided by the information resource 104 identifies which queuing path (amongst the plurality of queues 105) the packet is to be processed according to. Here, for example, certain queuing paths may be given unique rates of service as a vehicle for providing differentiated services to the packets that arrive to the networking machine 100. That is, for example, ingress packets that should experience reduced latency through the machine 100 (e.g., packets associated with a real time application such as a voice conversation or a video conference) may be placed into a queuing path that receives a high bandwidth rate of service; and, ingress packets that can experience a greater amount of latency through the machine (e.g., packets associated with a traditional data communication such as an email or an file transfer) may be placed in a queuing path that receives a low bandwidth rate of service.
The queuing paths of FIG. 1 have been grouped together (as queue(s) 105) for illustrative convenience. According to one approach, the “entire” packet (e.g., header and payload) is entered into its appropriate queuing path by the network processing logic 102. According to another approach, at least the payload of each ingress packet is stored into a separate memory device (not shown in FIG. 1 for simplicity) and a control header (e.g., a data structure that indicates where the packet payload may be found in the aforementioned memory device) is entered into its appropriate queuing path instead. For simplicity, either approach may be referred to as entering a packet into a queuing path.
Typically, after a packet is submitted into one of the queuing paths represented by queue(s) 105, it is eventually transported through the switching/routing circuitry 106 to another LIC (e.g., any of LICs 1012 though 101N) from where it is transmitted as an egress packet (e.g., along the LICs corresponding egress cable (e.g., cable 1082 for LIC 1012, etc., . . . , cable 108N for LIC 101N)). Note that if only a control header is entered into one of the ingress queues 105, it may be passed to the appropriate egress LIC; which, subsequently, uses the control header to fetch the packet (or whatever portion of the packet is needed to complete the packet). According to at least one design approach, the switching/routing circuitry 106 may direct the packet to the appropriate LIC based upon information that was retrieved from the look-up (e.g., the look-up performed by the network processing logic 102 may also produce an indication as to which LIC 1011 through 101N the packet is to be directed to). According to an alternative design approach, the switching/routing circuitry 106 “makes a decision” based upon the packet's header information.
2.0 Burst Write into Memory and Burst Read From Memory
FIG. 2a shows a Random Access Memory (RAM) unit 201 (e.g., a DRAM or SRAM). RAM memory units are traditionally managed by some form of control unit 202 (e.g., memory controller) that: 1) supplies addressing information (over address bus 203) to the RAM memory unit 201; and, 2) receives/sends data information from/to the memory unit 201 (over data bus 204). A “read operation” or a “read” are terms used to refer to the process by which data information is read from the RAM memory unit 201; and, a “write operation” or a “write” is a term used to refer to the process by which data information is written into the RAM memory unit 201.
According to traditional system design approaches, a system 205 that uses the RAM memory unit 201 (e.g., by sending write data along (and receiving read data from) system data bus 207) must supply an address to the control unit 202 (e.g., along system address bus 206) for each write operation and each read operation that is performed by the RAM memory unit 201. FIG. 2b shows the timing associated with such an approach. Here, at a first cycle 211, a first address 250 is provided to the control unit 202 by the system 205. At a second cycle 212, the address 250 is provided to the RAM memory unit 201 by the control unit 202 and information is read from or written into the RAM memory (depending on whether the operation desired by the system 205 is a write operation or a read operation). Here, as two cycles 211, 212 are consumed in performing a read or write operation, eight cycles will be consumed performing four consecutive read and/or write operations.
FIG. 2c shows an improved technique wherein accesses to the memory unit 201 are organized into “bursts” of accesses per address supplied by the system 205. Again, at a first cycle 221, a first address is provided to the control unit 202 by the system 205. In response, by comparison, a burst of four consecutive read or write operations (depending on whether the operation desired by the system 205 is a write operation or a read operation) is performed by the control unit 202 and RAM memory unit 201. As such, whereas eight cycles where consumed according to the approach of FIG. 2b, only five cycles are consumed according to the approach of FIG. 2c to perform the same number of read or write operations.
Here, the system 205 and control unit 202 can be designed with the understanding that the system 205 need only supply addresses to the control unit in the form of X . . . X00 (here each X can be either a 1 or a 0). Better said, the address supplied by the system 205 has its lowest ordered pair of bits set to “00”. Upon receipt of an address 251 from the system 205 by the control unit 202 (e.g., as drawn at the first cycle 221 of FIG. 2c), the control unit 202 applies this address 251 when actually addressing the memory unit 201 during the second cycle 222. However, during the third cycle 223 the control unit 202 automatically applies an address 252 of X . . . X01; during the fourth cycle 224 the control unit 202 automatically applies an address 253 of X . . . X10; and during the fifth cycle 225 the control unit 202 automatically applies an address 254 of X . . . X11.
Thus, the control unit 202 and system 205 have been designed with the understanding that memory accesses are performed in four cycle “bursts”. As such, the system 205 need not provide address values beneath a resolution of four; and, the control unit 202 is designed to automatically increment the address value 251 supplied by the system 202 with three increments (in one bit increments) over the course of the three cycles 223–225 following the cycle 222 where the address value 251 from the system has been applied to the RAM memory unit 201. Note that, from embodiment to embodiment, the number of accesses per burst may be other than four; and, each cycle may timed in accordance with one or more clock cycles. Furthermore, the RAM memory unit 201 may be multi ported (e.g., more than one data and address bus) rather than single ported as seen in FIG. 2a. 